What are the three triggering methods of triggers?

Three triggering methods of triggers: 1. Level triggering; when the trigger signal is a valid level (high or low), the input signal enters the trigger circuit and sets the trigger to the corresponding state. 2. Edge trigger refers to receiving input data when a certain agreed transition (positive transition or negative transition) of the clock pulse CLK arrives. 3. Pulse trigger.

The operating environment of this tutorial: Windows 10 system, Dell G3 computer.

The three triggering methods of flip-flops are: level trigger, edge trigger, and pulse trigger.

Level trigger

When the trigger signal is at a valid level (high or low), the input signal enters the flip-flop circuit and sets the flip-flop to the corresponding state. After the trigger signal becomes an invalid level, the input signal is blocked and the trigger state is maintained.

The status changes with the entire process of valid signals.

**Types of flip-flops: **Level-triggered SR flip-flop, level-triggered D flip-flop

# Level triggered action characteristics:

Only when CLK becomes a valid level, the flip-flop can accept the input signal and set the flip-flop to the corresponding state according to the input signal.

During the entire time when CLK=1, changes in S and R will cause changes in the state of the flip-flop output.

If the input signal changes multiple times during CLK=1, the state of the flip-flop will also flip multiple times.

This reduces the circuit’s ability to resist interference.

In a clock pulse cycle, the phenomenon of flip-flop flipping multiple times is called somersault.

Edge trigger

In order to improve the reliability of the trigger and enhance the anti-interference ability, it is hoped that the trigger will only depend on The state of the input signal reaches the moment when the falling edge (or rising edge) of the CLK signal arrives, and changes in the input state before and after this have no impact on the state of the flip-flop.

Edge triggering refers to receiving input data when a certain agreed transition (positive transition or negative transition) of the clock pulse CLK arrives. A flip-flop that does not receive data during CLK=l and CLK=0 and when non-conventional transitions of CLK arrive.

is only related to the status at that moment.

Types of flip-flops:

Use two levels to trigger an edge flip-flop composed of a D flip-flop, maintain a blocking flip-flop, and use gate circuit transmission delay Time edge trigger

##Trigger characteristics of edge trigger mode:

The secondary state of the flip-flop only depends on the rising edge (also called the positive edge) or falling edge (also called the positive edge) of the clock signal. The logic state of the input when a negative edge) arrives. In the past and in the future, changes in the input signal have no effect on the output state of the flip-flop.

This feature effectively improves the anti-interference ability of the trigger, thus also improving the working reliability.

Pulse trigger

Commonly used master-slave structure is implemented, that is, the master and slave flip-flops are connected in series, and the trigger signal is inverted. Taking the positive pulse trigger as an example, when the trigger signal is high, the input signal enters the main trigger and sets the main trigger state; after the trigger becomes low, the input signal is blocked and the main trigger state is maintained. At the same time, the slave trigger The status is determined based on the main trigger status.

The signal may only change once.

Type of trigger:

Master-slave SR trigger, master-slave JK trigger

#Pulse trigger action characteristics:

1. The flip of the trigger is divided into two steps.

The first step is that during CLK=1, the master flip-flop receives the input signal, while the slave flip-flop does not move;

The second step is that when the falling edge of CLK arrives, the slave flip-flop follows the master's The flip-flop state flips, so the change in the state of Q and Q' occurs on the falling edge of CLK (if CLK is a low-level active signal, the state change of Q and Q' occurs on the rising edge of CLK).

2. Because the main flip-flop itself is a level-triggered SR flip-flop, the input signal will control the main flip-flop during the entire time when CLK=1.

The difference between pulse triggering and edge triggering:

The pulse-triggered master-slave JK flip-flop cannot simply be judged by the J and K states at the falling edge of the clock. The state of Qn 1,

is as shown in the figure. During the high level of the clock, the states of J and K will change the logical relationship of the effective time. Originally, when J = K = 0 , Q remains unchanged.

It can be seen that the pulse-triggered master-slave trigger is susceptible to interference. It is not a practical trigger. It only introduces the development history of the trigger in the textbook, or part of the principle and structure of the trigger. You know That's all it takes.

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