The purpose of the adder using the carry-ahead is to speed up the transmission of the carry signal. The carry ahead is the carry generated by the high carry and the low carry at the same time; in the carry ahead adder, the carries at each level are generated independently of each other and are only related to the input data A, B and C_in, and the carry cascade between the levels is propagated to remove , it can reduce the delay caused by the carry and speed up the transmission of the carry signal.
The purpose of the adder using lookahead carry is to "accelerate the transmission of the carry signal."
The carry chain is a logical circuit that delivers carry. A lookahead carry is a carry generated by a high-order carry and a low-order carry at the same time. There are two types of lookahead carry, one is intra-group parallel and inter-group serial carry chain, the other is intra-group parallel and inter-group parallel carry chain, also known as parallel carry.
Carry-ahead adder. The carries at each level are generated independently of each other and are only related to the input data A, B and C_in. The carry cascade between the levels is removed, so that the carry can be reduced. The resulting delay. Each equation corresponds to a circuit with only three stages of delay. The first stage of delay corresponds to the carry generation signal and the carry transfer signal, and the last two stages of delay correspond to the sum of the above products. Adders implemented through this carry method are called carry-lookahead adders. Because each carry is generated in parallel, it is a parallel carry adder.
The carry-ahead adder avoids the carry delay of the traveling wave carry adder and improves the speed. Although it increases the carry-ahead part, it still takes up less resources than the carry-selective adder. Optimizing the design of basic unit circuits and their combination schemes and structures can further reduce resource (area) occupation, increase speed, and reduce power consumption. Determining the optimized basic unit circuits and their combination schemes will provide a basis for optimizing CLA structure design.
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