DDR5 MRDIMM and LPDDR6 CAMM memory specifications are ready for launch, JEDEC releases key technical details

This site reported on July 23 that the microelectronics standard setter JEDEC Solid State Technology Association announced on the 22nd local time that the DDR5 MRDIMM and LPDDR6 CAMM memory technical specifications will be officially launched soon, and introduced the key details of these two memories.

The "MR" in DDR5 MRDIMM stands for Multiplexed Rank, which means that the memory supports two or more Ranks and can combine and transmit multiple data signals on a single channel. Bandwidth can be effectively increased without the need for additional physical connections.

JEDEC has planned multiple generations of DDR5 MRDIMM memory, with the goal of eventually increasing its bandwidth to 12.8Gbps, doubling the current 6.4Gbps of DDR5 RDIMM memory.

In JEDEC’s vision, DDR5 MRDIMM will utilize the same pin, SPD, PMIC, etc. designs as existing DDR5 DIMM, be compatible with the RDIMM platform, and utilize the existing LRDIMM ecosystem for design and testing.

In addition, JEDEC has also planned the Tall MRDIMM form factor. As the name suggests, the design will feature a taller form factor that will double the number of DRAM packages it supports, further increasing memory capacity.

As for LPDDR6 CAMM, JEDEC said it is expected to achieve a maximum speed of more than 14.4GT/s, and will also mention 24bit wide sub-channel, 48bit Wide channel and supports "connector array" (note from this site: the original text is connector array).

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