Intel's next-generation LGA1851 socket pin definition and Core Ultra 200 series processor I/O specifications leaked

News from this site on July 2, blogger Jaykihn today broke the news about the pin definitions of Intel’s next-generation LGA1851 socket and the I/O specifications of Core Ultra 200 series processors such as Arrow Lake and Lunar Lake.

Intel Arrow Lake-S desktop platform:

SOC provided

PCIe Gen 5 x16

IOE provided

PCIe Gen 5 x4 + PCIe Gen 5 x4 (neither supports splitting)

PCH offers

PCIe Gen 4 x14

PCIe Gen 4 / SATA x7

PCIe Gen 4 / GbE x2

PCIe Gen 4 / SATA / GbEx1

USB2 x13

USB3 x10

The mobile Arrow Lake-HX platform provides one more USB 2.0 channel:

SOC provides

PCIe Gen 5 x16

IOE provides

PCIe Gen 5 x4 +PCIe Gen 5 x4 (neither supports splitting )

PCH offers

PCIe Gen 4 x14

PCIe Gen 4 / SATA x7

PCIe Gen 4 / GbEx2

PCIe Gen 4/ SATA/ GbEx1

USB2 x14

USB3 x10

Arrow Lake for mobile -H platform provides:

SOC provides

PCIe Gen 4 x12

IOE provides

PCIe Gen 5 x8 (split is not supported) + PCIe Gen 5 x8 (can be split into two x4)

PCH Provide

USB2 x10

USB3 x2

This site noticed that the low-power Lunar Lake platform (Core Ultra 200V) also provides support for UFS storage.

SOC offers

UFS x2

PCIe Gen 4 / GbE x1

PCIe Gen 4 x3

PCIe Gen 5 x4

USB 3.2 Gen 2x1 (10Gbps) x2

USB2 x6

USB3 x2

The first batch of products equipped with Core Ultra 200V series Lunar Lake processors are expected to be launched in the third quarter of this year.

The above is the detailed content of Intel's next-generation LGA1851 socket pin definition and Core Ultra 200 series processor I/O specifications leaked. For more information, please follow other related articles on the PHP Chinese website!