What is makefile in linux

In Linux, makefile is the compilation rule of a project file, which describes the compilation and linking rules of the entire project; it includes which files need to be compiled, which files do not need to be compiled, and which files need to be compiled first. Which files need to be post-compiled, which files need to be rebuilt, etc.

#The operating environment of this tutorial: linux5.9.8 system, Dell G3 computer.

1. What is Makefile

Makefile can be simply thought of as the compilation rules of a project file, describing the compilation and linking rules of the entire project.

An enterprise-level project usually has many source files. Sometimes they are classified into different directories according to functions, types, and modules. Sometimes multiple programs are stored in one directory. source code.

Makefle was born to solve the problem of how to compile some of the above codes. It defines a set of rules that determine which files should be compiled first, which files should be compiled later, and which files should be recompiled.

Everything involved in compiling the entire project can be described in the Makefile. In other words, Makefile can automate the compilation of our project projects without having to manually enter a bunch of source files and parameters every time.

The advantage of Makefile is that it can achieve "autonomous compilation". The entire project usually only needs onemakecommand to complete compilation, linking, and even more complex functions. It can be said that any Linux source program comes with a Makefile.

2. Advantages of Makefile

• Manage the compilation of the code, decide what files to compile, the compilation order, and whether recompilation is needed;

• Save compilation time. If the file changes, you only need to recompile this file without recompiling the entire project;

• once and for all. Makefiles usually only need to be written once and do not need to be changed too much later.

3. Naming rules

Generally speaking, it is OK to name the Makefile asMakefileormakefile, but many sources The name of the file is lowercase, so more programmers use the name of the Makefile because it can display the Makefile first.

If you name the Makefile with another name, such as Makefile_demo, it is also allowed, but you should use it in the following way:

make -f Makefile_demo

4. Basic rules

Makefile's basic rules are:

Series Objective: dependence

(TAB) rule

## Objective --> Target files that need to be generated

Dependencies--> Some files required to generate the target

Rules--> Means of generating target files from dependency files

tab -->

Each rule must start with tab, spaces are not allowed

For example, we often write gcc test.c -o test, Using Makefile, it can be written as:

test: test.c gcc test.c -o test

Among them, test in the first line is the target to be generated, test.c is the dependency, and the second line is the rule for generating test from test.c.

Sometimes there are multiple goals in the Makefile, but the Makefile will

set the first goal as the ultimate goal.

5. Working principle

Generation of target:

a. Check whether the dependent files in the rules exist;

b . If the dependent file does not exist, look for rules to generate the dependent file.

For example, in the picture above, the rule for generating calculator is gcc main.o add.o sub.o mul.o p.o -o, Makefil will check main.o first, Whether add.o, sub.o, mul.o, p.o exists, if not, it will look for rules to generate the dependency file.

For example, if the dependency of main.o is missing, the Makefile will look below to see if there are rules to generate main.o. When it finds that the rule gcc main.c -o main.o can generate main.o, it uses this rule to generate main.o, and then generates the ultimate goal calculator.

The whole process is to search for dependencies downwards, and then execute commands upwards to generate the ultimate goal.

Update of the target:

a. Check all the dependencies of the target. If any dependency is updated, regenerate the target;

b. If the target file is later than the dependent file, it needs to be updated.

For example, if main.c is modified, the main.o target will be recompiled. When main.o is updated, the ultimate target calculator will also be recompiled. The update of other files is also done by analogy.

6. Command execution

make:

Use this command to generate the target file according to predetermined rules.

If the name of the Makefile file is not Makefile or makefile, the

-foption should be added, such as:

make -f Makefile_demo

make clean:

Clear the intermediate files (.o files) and final target files generated during the compilation process.

If a file named clean exists in the current directory, this command will not be executed.

-->Solution: Pseudo target declaration: .PHONY:clean

Special symbols:

-: Indicates that even if an error occurs during the execution of this command, subsequent commands will continue to be executed. For example:

-rm a.o build/

@: indicates that the command will only be executed without echoing. When a general rule is executed, the executing rule will be printed out on the terminal. After adding this symbol, only the command will be executed and the executed rule will not be echoed. For example:

@echo $(SOURCE)

7. Ordinary variables

Variable definition and assignment:

Variables are directly used The definition can be completed by assigning a value, such as:

INCLUDE = ./include/

Variable value:

Surround it with brackets and add dollar sign, such as:

FOO = $(OBJ)

The system comes with variables:

is usually uppercase, such asCC, PWD, CFLAG,etc.

Some have default values, some do not. For example, the common ones:

CPPFLAGS: Options required by the preprocessor such as: -I

CFLAGS: Parameters used during compilation –Wall –g -c

LDFLAGS : The option used by the link library -L -l

The default value of the variable can be modified. For example, the default value of CC is cc, but it can be modified to gcc:CC=gcc

8. Automatic variables

Commonly used automatic variables:

Makefile provides many automatic variables, but the following three are commonly used. These automatic variables can only be used in commands in rules and cannot be used elsewhere.

$@ --> Target in the rule

$ First dependency condition in the rule

$^ --> Rule All dependency conditions in

For example:

app: main.c func1.c fun2.c

gcc $^ - o $@

where: $^ represents main.c func1.c fun2.c, $

Pattern rules:

Pattern rules use % in the target and dependency conditions to match the corresponding files, such as main.c, func1.c in the directory , func2.c three files, the compilation of these three files can be completed by one rule:

%.o:%.c

$(CC) –c $

This pattern rule means:

main.o is generated by main.c,

func1.o is generated by func1.c,

func2.o is generated by func2.c

This is the role of pattern rules, which can match all files in the directory at one time.

9. Function

makefile also provides us with a large number of functions, and the following two functions are also frequently used. It should be noted that all functions in themakefile must have a return value. In the following example, suppose there are three files main.c, func1.c, and func2.c in the directory.

wildcard:

is used to find files of a specified type in a specified directory. The following parameter is the directory file type, for example:

src = $ (wildcard ./src/*.c)

This sentence means: Find all files with the suffix .c in the ./src directory and assign them to the variable src.

After the command execution is completed, the value of src is: main.c func1.c fun2.c.

patsubst:

Matching replacement, such as the following example, is used to find all files ending in .c from the src directory and replace them with .o files, And assign it to obj.

obj = $(patsubst %.c ,%.o ,$(src))

Replace all files with a .c suffix in the src variable with .o.

After the command is executed, the value of obj is main.o func1.o func2.o

Specially, if you want to place all .o files in the obj directory, you can use the following method:

ob = $(patsubst ./src/%.c, ./obj/%.o, $(src))

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