The logic function of the D flip-flop is Qn 1=D; it is an information storage device with memory function and two stable states. It is the most basic logic unit that constitutes a variety of sequential circuits and is also a digital logic An important unit circuit in the circuit.
The operating environment of this tutorial: Windows 7 system, Dell G3 computer.
Logic function of D flip-flop: Qn 1=D.
D flip-flop is an information storage device with memory function and two stable states. It is the most basic logic unit that constitutes a variety of sequential circuits, and is also an important unit circuit in digital logic circuits.
It is widely used in digital systems and computers. The flip-flop has two stable states, namely "0" and "1". Under the action of a certain external signal, it can flip from one stable state to another.
The flip-flop has a flip-flop composed of an integrated flip-flop and a gate circuit. There are two triggering methods: level triggering and edge triggering. The former can be triggered when CP (clock pulse) = 1, while the latter is mostly triggered on the leading edge of CP (positive transition 0→1).
The secondary state of the D flip-flop depends on the state of the D end before triggering, that is, the secondary state = D. Therefore, it has two functions of setting 0 and setting 1.
For edge D flip-flops, since the circuit has a maintaining blocking effect during CP=1, the change in data state at the D terminal during CP=1 will not affect the output state of the flip-flop.
D flip-flops are widely used and can be used as digital signal registers, shift registers, frequency division and waveform generators, etc.
Extended information
The D flip-flop consists of 4 NAND gates, of which G1 and G2 constitute the basic RS flip-flop. When the level-triggered master-slave flip-flop works, the input signal must be added before the positive edge. If an interference signal appears at the input during the high level of CP, it is possible that the state of the flip-flop will be incorrect. The edge trigger allows the input signal to be added just before the CP trigger edge arrives.
In this way, the time for the input end to be interfered is greatly shortened, and the possibility of interference is reduced. Edge D flip-flops are also called sustain-blocking edge D flip-flops. An edge D flip-flop can be formed by connecting two D flip-flops in series, but the CP of the first D flip-flop needs to be inverted with a NOT gate.
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