Intel Architecture Code Analyzer (IACA) is a powerful, static analysis tool that provides valuable insights into the scheduling of instructions executed on modern Intel processors. Despite its end-of-life status in 2019, IACA remains a useful resource for analyzing code performance.
IACA allows for the analysis of code in C/C or x86 assembler. It operates in three modes:
To analyze code with IACA, you need to inject markers into the compiled binary.
C/C :
#include "iacaMarks.h" while (cond) { IACA_START /* Loop body */ /* ... */ } IACA_END
Assembly (x86):
; NASM usage of IACA mov ebx, 111 ; Start marker bytes db 0x64, 0x67, 0x90 ; Start marker bytes .innermostlooplabel: ; Loop body ; ... jne .innermostlooplabel ; Conditional branch backwards to top of loop mov ebx, 222 ; End marker bytes db 0x64, 0x67, 0x90 ; End marker bytes
IACA generates textual reports and Graphviz diagrams that detail the scheduling analysis. These reports highlight potential bottlenecks in instruction execution. For instance, the following output for a Haswell processor analysis identifies the front end and AGU ports as the performance bottlenecks:
Throughput Analysis Report -------------------------- Block Throughput: 1.55 Cycles Throughput Bottleneck: FrontEnd, PORT2_AGU, PORT3_AGU
IACA has a few limitations:
Despite its limitations, IACA provides valuable insights into instruction scheduling and can aid in optimizing code performance. However, for more recent analysis, consider using an alternative tool, such as LLVM-MCA.
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