Are x86 Loads and Stores Atomic?

Atomicity of Loads and Stores on x86

Despite the impression that memory operations in std::atomic rely solely on bus locking, atomic operations are actually executed within the cache.

Cache Coherence

Cache coherence ensures that all cores have a consistent view of memory. Cache lines are transferred between cores and memory in atomic chunks. This allows atomic operations to occur within the cache, without relying on external bus locking.

Aligned Operations

Aligned load and store operations up to 64 bits are guaranteed to be atomic on x86 processors. This is because aligned accesses can be transferred over data paths that are wide enough to accommodate the entire operation.

Unaligned Operations

Unaligned loads and stores can become non-atomic, as they may require multiple accesses to complete. For example, a load or store that crosses a cache-line boundary must be performed in two separate accesses, making it non-atomic.

Atomic Read-Modify-Write Operations

Atomic read-modify-write operations, such as lock add [mem], eax, are more complex to implement than simple loads or stores. These operations require the core to hold the affected cache line in a modified state and prevent any external modifications until the operation is complete. Unaligned read-modify-write operations may require asserting the LOCK# signal to lock the bus and prevent other cores from accessing the affected memory.

Compiler Optimization

Compilers may optimize seq_cst loads by omitting the mfence instruction, as x86 memory ordering prevents LoadLoad and LoadStore reordering. However, fences are still necessary for seq_cst stores to prevent StoreLoad reordering.

In summary, atomicity on x86 processors is achieved through a combination of cache coherence, aligned operations, and bus locking for unaligned read-modify-write operations. This allows atomic operations to occur efficiently and without affecting the overall system performance.

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