Does adding unnecessary memory barriers improve visibility performance for atomic operations in producer-consumer queues?

Does Hardware Memory Barrier Enhance Visibility Performance for Atomic Operations?

Question:

In a producer-consumer queue, can adding unnecessary memory fences or stronger memory order improve the visibility of atomic operations? If so, what is the latency difference with and without a fence?

Answer:

Effects on Inter-Core Latency:

• Memory fences do not significantly impact inter-core latency for store operations.

Store Buffer Behavior:

• CPU store buffers are designed to commit writes to cache as quickly as possible. Fences only force the current core to wait for store completion, which would happen eventually without the fence.

Potential Secondary Effects:

• Fences may have minor secondary effects by blocking later loads and promoting invalidation of cache lines, possibly reducing miss penalties for subsequent loads on other cores. However, these effects are insignificant.

Load Performance:

• CPUs prioritize demand loads over other memory accesses. Adding barriers before or after loads generally does not improve performance.

Conclusion:

In most cases, adding unnecessary fences or stronger memory order will not improve visibility performance. Only very specific situations, involving pointer chasing and high load traffic, may see a negligible benefit. Empirical profiling is recommended to determine the optimal strategy.

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